In a paper entitled, "A 150-MHz Direct Digital Frequency Synthesizer in 1.25-.mu.m CMOS with--90-dBc Spurious Performance" by H. T. Nicholas et al. in IEEE Journal of Solid-State Circuits, Vol. 26, No. 12, December 1991 the authors explain that many direct digital frequency synthesizers use the modulo 2.sup.K overflow property of a K-bit word accumulator to generate the phase argument of a generated output wave. Successive words of the accumulator may be mapped into successive phase values for a generated output wave.
In U.S. Pat. No. 5,656,958 P. Albert et al. use a variation of the accumulator technique described above in a frequency synthesizing device for use in digital communications where the carrier frequency is to be established with great precision. The patent discloses a circuit which employs a phase lock loop to operate on an incoming data signal. An accumulator circuit receives a digital word from a source. A variable divider circuit processes accumulator output signals to adjust the phase of the local clock based upon the contents of the digital word. Continuous changes of phase of the local clock give rise to changes in output frequency.
The circuit disclosed by P. Albert et al. is useful for the situation where a digital channel contains a subchannel or slot in which phase information of the clock is encoded with a digital word. For example, in MPEG (Motion Picture Expert's Group) data transmission, there is a subchannel known as the system clock reference (SCR) which is transmitted at least as often as every 0.7 second by the MPEG encoder. The SCR signal must be received, decoded and sent to the audio and video decoders to update internal clocks. The subchannel may be used to encode a number for use in a frequency synthesizer.
Phase lock loops are well known circuits for locking the phase of a clock signal. A phase lock loop can cancel the jitter, i.e. short term variations of the significant edges of a digital signal, which occurs in the transmission channel. Such clock recovery circuits are described in U.S. Pat. No. 4,241,308 to A. Lovelace et al.
An object of the invention was to synthesize a frequency near a reference frequency using digital techniques, with high stability and low jitter. Another object is to provide the last stage of a phase lock loop, namely a numerically controlled oscillator.